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Start of the W&T |
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| 8:30-9:00 | John Davis (BSC) - bio | Welcome and MEEP - abstract - slides |
| Session 1 / Chair: John Davis (BSC) | ||
| 9:00-9:30 |
Dan Petrisko (U. of Washington) - bio |
BlackParrot: An Agile Open Source RISC-V Accelerator Host Multicore - abstract - slides |
| 9:30-10:00 |
Andrea Bartolini (U. of Bologna) - bio |
RISC-V open-ISA and open-HW - a Swiss army knife for HPC - abstract - slides |
| 10:00-10:30 |
Anton Blanchard (Open Source Technology leader / Sydney, Australia OpenPOWER) - bio and Tristan Gingold (CERN) - bio |
Microwatt and GHDL - An Open Hardware CPU written in VHDL, synthesized with Open Source tools - abstract - slides Tristan Gold slides |
| Coffee break | ||
| Session 2 / Chair: Alexander Fell (BSC) | ||
| 11:00-11:30 | Borja Pérez (BSC)- bio | Spike+Sparta: Developing a scalable RISC-V simulation infrastructure for HPC architectures. abstract - slides |
| 11:30-12:00 | Osman Unsal (bio) and Adrián Cristal (BSC) - bio | Designing open-source RISCV hardware with open-source software - abstract - slides |
| 12:00-12:30 |
Frank K. Gürkaynak (ETH Zurich) - bio |
Seven stories from seven years of PULP project - abstract - slides |
| 12:30-13:00 |
Roger Espasa (SemiDynamics) - bio |
Hardening an academic core for industrial use - abstract - slides |
| Lunch break | ||
| Session 3 / Chair: Borja Pérez (BSC) | ||
| 14:00-14:30 |
Brian Thompto (IBM Distinguished Engineer / IBM Systems / Austin OpenPOWER) - bio |
The Open Power ISA: A Summary of Architecture Compliancy Options and the Latest Foundations for Future Expansion - abstract - slides |
| 14:30-15:00 |
Jose Moreira (IBM Research / NY OpenPOWER) - bio |
Advanced High-Performance Computing Features of the OpenPOWER ISA - abstract - slides |
| 15:00-15:30 | Francesc Moll (bio) and Miquel Moretó (BSC) - bio |
Building the Road from Computer Architecture to Silicon at BSC - abstract - slides |
| Coffee break | ||
| Session 4 / Chair: Miquel Moretó (UPC / BSC) | ||
| 16:00-16:30 |
James Kulina (Executive Director OpenPOWER) - bio |
OpenPower Foundation Update: New leadership and a bright open future - abstract - slides |
| 16:30-17:00 |
Calista Redmond (CEO RISC-V International) - bio |
Growing RISC-V momentum around the world, in multiple disciplines, and across industries - abstract - slides |
| 17:00-17:30 |
Krste Asanovic (UC Berkeley/SiFive) - bio |
RISC-V for HPC - abstract - slides |
| 17:30-18:00 |
Jonathan Balkind (Princeton U.) - bio |
Enhancing the Open-Source P-Mesh Cache Coherence System for Open ISAs - abstract - slides |
| 18:00-18:30 | John Davis (BSC) |
Wrap-up - Slides |
Biographies and Abstracts
| NAME | BIO | TALK TITLE | ABSTRACT |
| John D. Davis | John D. Davis is the director of LOCA, the Laboratory for Open Computer Architecture, and the PI for MEEP at the BSC. He has published over 30-refereed conference and journal papers in Computer Architecture (ASIC and FPGA-based domain-specific accelerators, non-volatile memories and processor design), Distributed Systems, and Bioinformatics. He also holds over 35 issued or pending patents in the USA and multiple international filings. He has designed and built distributed storage systems in research and as products. John has led the entire product strategy, roadmap, and execution for a big data and analytics company. He has worked in research at Microsoft Research, where he also co-advised 4 PhDs, as well as large and small companies like Sun Microsystems, Pure Storage, and Bigstream. John holds a B.S. in Computer Science and Engineering from the (University of Washington) and an M.S. and Ph.D. in Electrical Engineering (Stanford University). | Welcome and MEEP | In this talk, we will discuss a unique infrastructure project being built at the BSC to help support the hardware and software development for RISC-V based systems. This is the first research project to be associated with a supercomputer procurement and will use FPGAs to develop a pre-silicon validation and software development vehicle. This is a combination of host servers and many FPGAs (up to 8 per server) used to emulate an HPC system. This enables system-level software development and testing. This platform can be the basis for many other research projects focused on CPU and accelerator design. |
| Dan Petrisko | Dan Petrisko is a Ph.D. student in the Paul G. Allen School of Computer Science and Engineering at the University of Washington. He is the lead developer on the BlackParrot project. His research interests focus on the software engineering of hardware, designing flexible microarchitectures, and agile test chip tapeouts. Dan received his B.S and M.S in Computer Engineering from UIUC, where he researched wafer-scale systems. | BlackParrot: An Agile Open Source RISC-V Accelerator Host Multicore | The end of Dennard scaling has led to a Cambrian explosion of energy-efficient, specialized silicon in everything from embedded microcontrollers to massive HPC systems. However, these heterogeneous clusters still require general-purpose processors to manage, monitor and coordinate their accelerators. An ideal host core is efficient, performant, and reliable; able to support a diverse array of accelerators without creating new bottlenecks; and is free and open-source, so that architects can rapidly design, prototype and verify their systems. BlackParrot aims to be the default open-source, Linux-capable, cache-coherent, RISC-V multicore used by the world. Development efforts prioritize ease of use and silicon validation as first order design metrics, so users can quickly get started and trust their results will be representative of state-of-the-art ASIC designs. In this talk, we will provide an architectural overview of BlackParrot, focusing on the design principles and development process as well as the software and hardware ecosystems surrounding the core. We will also discuss different accelerator integration strategies supported, as well as our plans to engage the community to ensure BlackParrot is the optimal "base class" for accelerator-based SoCs. |
| Andrea Bartolini | Andrea Bartolini received a Ph.D. degree in Electrical Engineering from the University of Bologna, Italy, in 2011. He is currently an Assistant Professor in the Department of Electrical, Electronic, and Information Engineering (DEI) at the University of Bologna. Before, he was a Post-Doctoral researcher in the IIS Laboratory at ETH Zurich. Since 2007 Dr. Bartolini has published more than 100 papers in peer-reviewed international journals and conferences with a focus on energy efficiency for embedded and HPC systems | RISC-V open-ISA and open-HW - a swiss army knife for HPC | To cope with the steaming out of Moore’s law and Dennard’s scaling end, the world of High-Performance Computing is rapidly evolving toward high-throughput architectures with specialized hardware for vectors and tensor operations in conjunction with sophisticated power management subsystems. RISC-V ISA and Open-HW can prove its effectiveness in fostering innovation in the HPC market as it has done in the embedded one. In this talk, I will introduce a set of building blocks for future HPC systems we have been designing at the ETH Zurich and the University of Bologna. |
| Anton Blanchard | Anton has been involved with Linux and Open Source Software for over 20 years, much of that time with IBM. He leads a worldwide team dedicated to using Open Source technologies to build better products. In mid-2019, he got the Open Hardware bug as a result of IBM's opening up of the POWER ISA. | Microwatt and GHDL - An Open Hardware CPU written in VHDL, synthesized with Open Source tools
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Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux.
From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project. |
| Tristan Gingold | Tristan Gingold has developed GHDL, the main open-source VHDL simulator, for about 20 years. He is currently working at CERN in the hardware and timing section. | Microwatt and GHDL - An Open Hardware CPU written in VHDL, synthesized with Open Source tools | Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux.
From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project. |
| Borja Pérez |
Borja Perez is a performance modeling engineer for the MEEP project in BSC. His research interests include computer architecture, memory hierarchy and heterogeneous systems. He received his B.S. and Ph.D. degrees in Computer Science and Engineering from Universidad de Cantabria (Spain).
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Spike+Sparta: Developing a scalable RISC-V simulation infrastructure for HPC architectures
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Early stages of hardware design involve high-level decisions that determine the flavor of the overall architecture. These kind of decisions need to be informed by data. However, when designing hardware with high core counts and complex memory hierarchies, the simulation time of high detail tools ranges from impractical to unfeasible. This talk introduces some early experiences of integrating the Spike RISC-V functional simulator with the Sparta architecture simulation toolkit, to build an infrastructure for fast simulation of future HPC processors. |
| Adrián Cristal |
Dr. Adrián Cristal is co-manager of the Computer Architecture for Parallel Paradigms research group at BSC. His interests include high-performance microarchitecture, multi- and many-core chip multiprocessors, transactional memory, and programming models. He received a Ph.D. from the Computer Architecture Department at the Polytechnic University of Catalonia (UPC), Spain, and he has a BS and an MS in computer science from the University of Buenos Aires, Argentina. |
Designing open-source RISCV hardware with open-source software | In this talk, we are planning to discuss our experience with using open source software at the architecture, microarchitecture, RTL, and verification levels for designing and taping out RISCV accelerators. In particular, we would like to discuss about the GEM5 based microarchitectural simulator that we developed towards designing a vector accelerator core; as well as the application suite that enables us to benchmark vector processors. |
| Osman Unsal |
Dr. Osman Unsal received the B.S., M.S., and Ph.D. degrees in Electrical and Computer Engineering from Istanbul Technical University (Turkey), Brown University (USA), and the University of Massachusetts, Amherst (USA) respectively. Together with Dr. Adrian Cristal, he co-manages the Computer Architecture for Parallel Paradigms research group at BSC. His current research interests include many-core computer architecture, reliability, low-power computing, programming models, and transactional memory. |
Designing open-source RISCV hardware with open-source software | In this talk, we are planning to discuss our experience with using open source software at the architecture, microarchitecture, RTL, and verification levels for designing and taping out RISCV accelerators. In particular, we would like to discuss about the GEM5 based microarchitectural simulator that we developed towards designing a vector accelerator core; as well as the application suite that enables us to benchmark vector processors. |
| Frank K. Gürkaynak | Frank is the director of Microelectronics Design Center that supports IC, FPGA, and PCB design within ETH Zurich and works as a Senior Scientist in the group of Luca Benini supporting him in running the group. He has been part of PULP project since its beginning. | “Seven stories from seven years of PULP project” | PULP project started in 2013 and from the beginning decided to keep its development open source. In this time we have achieved notable successes and we are very proud to see that PULP project has contributed to research and even found success in commercial environments. At the same time, we also faced challenges we did not expect when we started seven years ago. In this talk, I will look back and based on seven different ASICs from our PULP project and tell the story of how our open source approach has shaped the way we work. I will concentrate on opportunities for collaboration and discuss still open problems that we are trying to solve. |
| Roger Espasa |
Roger Espasa got his PhD in Computer Science from Universitat Politècnica de Catalunya in 1997. Between 1999 and 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture (see the Tarantula paper). In 2002, the Alpha team was acquired by Intel. Between 2002 and 2014 Roger worked at Intel developing a vector extension for the x86 ISA, which was initially deployed in the Larrabee and Knight's Corner product and then became the AVX-512 extension. Roger also led the team implementing the texture sampling unit for the original Larrabee chip. Roger also worked on the core for the Knight's Landing product (14nm) and led the core for the follow-on Knights Hill 10nm product. In 2014, Roger joined Broadcom where he worked on a from-scratch ARMV8 wide out-of-order core supporting both A64 and A32. In 2016, Roger founded SemiDynamics Technology Services. From 2016 to 2019, Roger was Esperanto Technologies chief architect, where he developed a 7nm architecture for machine learning. Additionally, from 2018 onward, Roger is leading the design of the Avispado RISC-V core, targeted at high-bandwidth applications and supporting an open vector interface to vector processing units. |
Hardening an academic core for industrial use | In this talk, we will discuss the strategies and challenges of using an open-source academic core and hardening for industrial use. We'll touch on the microarchitectural areas that require the most attention from a functional point of view as well as the areas that need performance improvements. We'll use as examples a couple of very popular open-source academic cores, Rocket and Ariane |
| Brian Thompto |
Brian W. Thompto is an IBM Distinguished Engineer based in Austin, TX. He is the chief core architect for IBM POWER servers and recently led the architecture and design of the processor core for POWER10, IBM's next generation server. He has over 20 years of experience leading global development teams across 10 generations of IBM POWER and IBM System z processors. His prior roles included being a lead architect and the overall performance leader for the POWER9 processor, the CPU powering the Summit and Sierra supercomputers. Mr. Thompto is an IBM Master Inventor with over 100 patent applications granted or pending. He received a B.S. degree in electrical engineering and a second major in computer science from the University of Wisconsin-Madison in 1999. |
The Open Power ISA: A Summary of Architecture Compliancy Options and the Latest Foundations for Future Expansion | The Open Power ISA enables access to unencumbered open innovation and a mature software ecosystem developed over the last 30 years. In this talk, we will review the major options for architectural compliancy that provide freedom of choice in design, including four recently specified compliancy subsets, separate optional features, and custom extensions. IBM has also recently contributed the Power ISA Version 3.1 to the Open Power ISA. This latest architectural version includes a number of new features developed for the POWER10 server including a new foundation for future expansion via the introduction of an instruction prefix. New capabilities and compliancy implications will be summarized. |
| José Moreira | José E. Moreira is a Distinguished Research Staff Member in the Scalable Systems Department at the Thomas J. Watson Research Center. He received a B.S. degree in physics and B.S. and M.S. degrees in electrical engineering from the University of Sao Paulo, Brazil, in 1987, 1988, and 1990, respectively. He also received a Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 1995. Since joining IBM at the Thomas J. Watson Research Center, he has worked on a variety of high-performance computing projects. He was system software architect for the Blue Gene/L supercomputer and chief architect of the Commercial Scale Out project. He currently leads the IBM Research work on the architecture of POWER processor. He is an author or coauthor of over 100 technical papers and 15 US patents. Dr. Moreira is a Senior Member of the IEEE (Institute of Electrical and Electronics Engineers) and a Distinguished Scientist of the ACM (Association for Computing Machinery). | Advanced High-Performance Computing Features of the Open Power ISA | Power ISA processors have a long history of offering superior features for HPC applications. Well known examples include POWER3, used in the ASCI White supercomputer, various PowerPC processors used in the Blue Gene family of massively parallel computers, and POWER9, present in the leading supercomputers of today, Summit and Sierra. Open Power ISA has enabled open access to many of these features. IBM's most recent contribution to Open Power ISA, in the form of Power ISA Version 3.1, includes the Matrix-Multiply Assist (MMA) instructions. The MMA instructions are designed to deliver additional performance both for classical high-performance computing, in the space of scientific and technical computing, and for the increasingly important space of business analytics. In addition, the Open Memory Interface (OMI), also developed by IBM, opens new levels of memory bandwidth and capacity for the most demanding applications. Our goal is to raise awareness of and interest in these new features, which we believe can lead to further research in processor architecture and programming environments. Some of the most promising application areas include graph algorithms, classical machine learning and deep learning |
| Francesc Moll | Francesc Moll is a professor in the Department of Electronic Engineering of the Universitat Politècnica de Catalunya (UPC) since 1997, and he collaborates with BSC since 2018. He received in 1991 the equivalent of the M.Sc. degree in physics from the University of Balearic Islands, Spain, and in 1995 the Ph.D. degree in Electronic Engineering from UPC. His research career has been focused on reliability and robustness issues relevant to integrated circuit design especially in advanced technology nodes, such as signal integrity modeling and its impact, manufacturing variability and ultra-low power and voltage circuits. He teaches several integrated circuit design courses in the Electronic Engineering Master at UPC. At BSC, he participates in the DRAC and EPI projects within the synthesis and physical design team. https://scholar.google.com/citations?user=BdCE6vkAAAAJ&hl=en |
Building the Road from Computer Architecture to Silicon at BSC | This talk explains the different projects related to integrated circuit design (IC) currently going on at BSC. These projects are an opportunity and a challenge in terms of building a new team, including the incorporation of key senior experts in the field, leveraging previous expertise from nearby academic institutions and training young people in backend IC design techniques. The structure of the newly formed team and toolset will be explained, as well as the roadmap of design techniques under development at BSC in the framework of ongoing projects |
| Miquel Moretó | Miquel Moretó is a Ramón y Cajal Researcher at UPC and an associate researcher at the Barcelona Supercomputing Center (BSC). Prior to joining UPC, he was a Fulbright Postdoctoral Research Fellowship Holder at the International Computer Science Institute (ICSI), affiliated with UC Berkeley, from 2012 to 2013. He received the B.Sc., M.Sc., and Ph.D. degrees from UPC. His research interests include high performance computer architectures and hardware-software co-design for future massively parallel systems. ## webpage: http://personals.ac.upc.edu/mmoreto/ |
Building the Road from Computer Architecture to Silicon at BSC | This talk explains the different projects related to integrated circuit design (IC) currently going on at BSC. These projects are an opportunity and a challenge in terms of building a new team, including the incorporation of key senior experts in the field, leveraging previous expertise from nearby academic institutions and training young people in backend IC design techniques. The structure of the newly formed team and toolset will be explained, as well as the roadmap of design techniques under development at BSC in the framework of ongoing projects |
| James Kulina |
James is Executive Director of the OpenPower Foundation, with over 10 years of open source experience across hardware, software, and network engineering disciplines. James brings a passion for open source and is committed to growing OpenPower Foundation membership, community, and ecosystem.He is a seasoned entrepreneur with a background in enterprise technology. He has worked in roles spanning operations, business development, product management and engineering. |
OpenPower Foundation Update: New leadership and a bright open future | The opening up of the POWER ISA in 2019, set OpenPower Foundation on a new course, paving the way for a bright and open future. This talk will introduce James Kulina, the new Executive Director for the OpenPower Foundation, as well as provide attendees a summary of the latest developments within the OPF community. The presentation will touch on what's ahead for OpenPower Foundation as it further integrates and strengthens its collaboration with other Linux Foundation projects. |
| Calista Redmond | Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included the execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University. |
Growing RISC-V momentum around the world, in multiple disciplines, and across industries | RISC-V has opened opportunity and ignited innovation in HPC. As an open specification, RISC-V has created a foundation for custom processing without the proprietary challenges of traditional architectures. Stemming from an open base ISA and growing with numerous extensions, engineers are designing specific processors to tackle diverse HPC demands, from oil and gas exploration to safeguarding nations, from navigating air and space to genome sequencing. Taking an open approach through the RISC-V community has opened both technology collaboration as well as diminished traditional business barriers. With global, regional, and local support, RISC-V is accelerating HPC in Europe |
| Jonathan Balkind |
Jonathan Balkind is a Ph.D. Candidate in Computer Science at Princeton University. His research interests lie at the intersection of Computer Architecture, Programming Languages, and Operating Systems. He is the Lead Architect of OpenPiton and its heterogeneous-ISA descendent, BYOC, which are productive research platforms with thousands of downloads from over 70 countries worldwide. Jonathan received an M.A. from Princeton University and an MSci from the University of Glasgow. |
Enhancing the Open-Source P-Mesh Cache Coherence System for Open ISAs | P-Mesh is the manycore cache coherence system underlying the OpenPiton research platform, which originally used the SPARCv9 ISA. A number of extensions to P-Mesh were needed to build the Bring Your Own Core (BYOC) platform, which added support for cores using new, open ISAs like RISC-V. In this talk, we will introduce P-Mesh and the changes we are making to turn it into an ISA-agnostic memory system. We will detail the specific changes needed to support RISC-V, our new interface for connecting cores, and our initial efforts to support cores using the OpenPOWER ISA. We will also discuss our efforts to connect multiple cores of different ISAs to build a single heterogeneous-ISA system. |
| Krste Asanovic | Krste Asanovic is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Par Lab, and then led the ASPIRE lab. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Co-Director of the Berkeley ADEPT lab, tackling the challenge of creating and deploying specialized processors, and is also an Associate Director at the Berkeley Wireless Research Center. He leads the free RISC-V ISA project at Berkeley, is Chairman of the RISC-V Foundation, and is Chief Architect and a co-founder at SiFive Inc. He is an ACM Fellow and an IEEE Fellow. | RISC-V for HPC | The end of Dennard scaling over a decade ago has led to increased interest in specialized architectures to continue performance scaling. In response to this trend, RISC-V was developed as a free and open modular ISA, providing a small, efficient, extensible base to which domain-specific extensions can be added. The new RISC-V vector extension provides a highly scalable vector architecture well suited to classic HPC problems and also to new challenge areas in AI and machine learning. Unlike other ISAs, RISC-V can provide a uniform software environment across both custom accelerators and general-purpose cores in a HPC computing platform. While RISC-V shows a lot of promise, it is still a new and rapidly developing technology. In this talk, I'll cover the opportunities and challenges for RISC-V in the HPC space. |